Comparison of Parallel and Deductive Fault Simulation Methods

A comparison of the central processing unit (CPU) time and storage requirements for the parallel and deductive fault simulation techniques is presented. Versions of a parallel and deductive simulator were implemented and the comparison performed on an IBM System/360 Model 67 by simulating representative circuits including shift registers, sequencers, counters, two memory units, and a processor. The results indicate that the deductive technique requires less CPU time for "loosely sequential" circuits or circuits having large numbers of simulated faults (e.g., >1000). The paraUel technique is faster for small (e.g., < 500 gates) "highly sequential" circuits or for small numbers of simulated faults. Manuscript received November 9, 1973; revised May 7, 1974. H. Y. Chang, S. G. Chappell, and C. H. Elmendorf are with Bell Laboratories, Naperville, Ill. 60540. L. D. Schmidt was with Bell Laboratories, Naperville, Ill. 60640. He is now with McDonnell Douglas Automation Company, St. Louis, Mo. 63166. The storage required for a parallel simulator, however, can always be less than that required for a deductive simulator. In general, if sufficient memory is available, the deductive simulator is the more cost-effective simulator when a wide range of circuits is to be simulated and only one type of simulator is available. A substantial savings in logic circuit development cost can be realized when the proper simulation technique is used for logic design verification, fault analysis, and the generation of diagnostic data.